In the rapidly advancing semiconductor manufacturing industry, complementary metal oxide semiconductor (CMOS) FinFET devices are increasingly used in many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed. A gate is formed over and along the sides of a portion of the semiconductor fins. The use of fins increases surface areas of the channel and source/drain regions for the same area. The increased surface area of the in a FinFET results in faster, more reliable and better-controlled semiconductor transistor devices that consumes less power.
New advanced designs are created with FinFET structures at the outset with computed-aided design (CAD) layers that define the boundary of each FinFET. As manufacturing process progresses into smaller and smaller technology nodes, devices originally designed in a larger technology node may benefit from manufacturing in a smaller technology node in ways such as increased performance and efficiencies and decreased die size. Similarly, devices designed using planar transistors can also reap benefits by manufacturing using FinFETs. However, because different design rules apply to planar structure layouts and FinFET structure layouts, converting portions of the device from a planar layout to a FinFET layout by hand may be akin to creating a new design and is a highly resource intensive process. For product already being manufactured using planar transistors, a conversion that includes changes to semiconductor layers above the transistor level would require many new photomasks to be created, which dramatically increases manufacturing cost.
As such, improved methods for automatically converting planar structure layouts to FinFET structure layouts continue to be sought.